Thank you for using Intel Ethernet. There are a couple of things in your post that make me want to ask you to double check some of your algorithms. First is that for Intel Ethernet controllers you do not write directly into the chip FIFO, rather, you will describe your Ethernet frame in your transmit descriptor ring including the buffer address(s) for the actual data. Writing the descriptor ring tail doorbell from your driver will then result in the networking silicon to DMA the frame from host memory and transmit out on the wire. You can see these flows in the data sheet section 7.2:
Secondly, you mention the FIFO address of 0x5B00 which if you were referring to a register on the silicon, but when I look into the datasheet that register address is for one of our PCI Express registers.
Thanks for your inputs.
We had done almost all the things specified by you, like writing to descriptor ring tail etc. Now most of things are working.
Earlier we had a problem, i.e., when we were trying to ping the system where the ethernet controller is connected, reply to the ping request for data over 900 bytes was failing.
Now we have resolved it by configuring the PCIe Configuration Register Device Control, Offset 0xE8, (RW) to a value 0X0810(resized Max Read Request Size to 128 bytes).
Now the problem that we are facing is whenever my ethernet controller is connected over 1 GBPS n/w, a ping request for over 900 bytes timesout sometimes and passes sometimes, i would like to know are we failing to intialize any configuration registers, or this is some other problem??
Thanks in advance,