3 Replies Latest reply on Jun 14, 2011 5:24 AM by kamesh

    SCC Performance Measurements

    tedk

      There’s recently been some interest in SCC performance measurements.  There’s also been some confusion about what performance measuring features are available on the SCC.

       

      It’s important to note that the SCC has P54C cores. The SCC belongs to the P5 family processors. Sometimes you may see the cores referred to as Gauss Lake cores. The differences between the P54C and Gauss Lake are minor. Gauss Lake has a larger L1 cache, a new memory type (MPBT), and a new instruction that flushes MPBT data from L1.

       

      Performance monitoring capabilities are tied to the implementation dependent aspects of a particular processor. If you read one of the newer Pentium manuals, you will unfortunately get some misinformation. The best manual to read for a description about performance monitoring on the SCC is the 1995 Pentium Processor Family Developer’s Manual, which is posted on this site. Please look at Chapter 26.

       

      With P6 came the ability to generate local APIC interrupts on counter overflow.  This ability is not present in P5 family processors. For example, you can read in the Software Developer’s Manual Volume 3B:System Programming Guide, Part 2 in Section 30.16.5 that the P6 family processors provide the option of generating a local APIC interrupt when a performance-monitoring counter overflows. The SCC, however, belongs to the P5 family.

       

      You still have access to performance counters. With the new Linux kernel (not yet available) you will have easier access. Some users have already begun performance measurements. Please look at http://communities.intel.com/message/117248#117248 .  That thread has a description of work by Andrea Bartolini, Thomas Prescher, and Junghyun Kim. You can use the msr tools. CPUID shows that WRMSR and RDMSR are supported. Note that it also shows that MMX (also called SSE) is not, indicating that SCC is a member of the P5 family.

       

      Here’s the output from a short program (source attached) that runs on a core and parses some information from the CPUID.

       

      root@rck00:/shared/username/CPUID> ./cputest

      System contains a genuine Intel processor ...

      System allows WRMSR and RDMSR...

      System does not support MMX

      root@rck00:/shared/username/CPUID>

        • 1. Re: SCC Performance Measurements
          kamesh

          Is there any info on when the new linux kernel becomes available? I have been attempting to read the msr's but with little success. The msr-tools fail to execute when attempting through rccerun on the mcpc and through sccKonsole. Rccerun exits with error code 139 and in sccKonsole I get a "

          rdmsr: open: No such file or directory". I have also been creating a simple C program that writes 11h into ECX before running rdmsr. With rccerun the program returns with an error code 139 and when using sccKonsole to sudo the program I get a segmentation fault. Is there any help to this problem in the new kernel or is there any info on correctly accessing these registers?

          • 2. Re: SCC Performance Measurements
            Enric

            Just unpack the msr.tar.gz in the /shared folder and type in the terminal of the scc core

            root@rck00:/shared>./install_msr.sh

             

            Then you will be able to use  rdmsr and wrmsr normally in that core.

            However you need to install it every time you reload the image.

            • 3. Re: SCC Performance Measurements
              kamesh

              Thank you, i managed to get it working and have been successfully working with the registers.