9 Replies Latest reply on Mar 4, 2011 6:57 PM by websrvr

    QPI register information

    websrvr

      I've been looking for information on the QPI registers.

       

      What I am specifically interested in is reading the QPI interlink speed (4.8, 5.8 and 6.4).

       

      I have already discussed this with someone who detects this but unfortunately he wont share the secret.

       

      I have been able to figure out how to unhide the QPI device and I thought I could just read a register to get the speed but I can't seem to locate a breakdown of the registers showing what bytes I need to check to get this information.

       

      I'm not interested in calculating the current interlink speed, just finding the rated speed, what I know is an i7-920 and i7-930 have an interlink speed of 4.8GT and a i7-980X has an interlink speed of 6.4GT (because I have these CPU's) and I was hoping there was an easy way to get this from from all the CPU's.

        • 1. Re: QPI register information
          Doc_SilverCreek

          I assume you don't just want to go to http://ark.intel.com/?wapkw=(ark) and look up the specific processor link speeds?

          • 2. Re: QPI register information
            Doc_SilverCreek

            You can also check the processor spec sheet.

            i.e. Page 42 for the 56xx Xeon processors.

            http://www.intel.com/Assets/en_US/PDF/datasheet/323370.pdf

            • 3. Re: QPI register information
              websrvr

              I need to detect the interlink in order for my EFI boot loader to use the information or are you saying that there is no register and that I should hard-code the information for W3520/i7-920 and force the user to buy one of these if they want to boot linux under EFI?

               

              At this point discussing why I need to detect the speed serves no purpose other than explaining to you why I need to do it so just accept that this information is required and is then passed by the boot loader to the kernel along with a handful of other information and sending the incorrect information affects clocks and timings so either I support all CPU's by detecting it's interlink and calculating clocks or only a specific CPU by hard-coding the interlink and calculating the clocks.

               

              I'm told that there is a register with this information however the person who knows is not willing to share the information so currently I can only EFI boot linux with a W3520/i7-920 until I can detect the interlink because I hard-code the information.

               

              True EFI booting requires a graphics card with EFI firmware and is easy to add to most nVidia (some require an SPROM change to increase space for the EFI and legacy firmware) and ATI (I have yet to find one that doesn't support EFI and legacy firmware) cards.

               

              Most SAS controllers already come with EFI and legacy firmware and I have experienced no issues with any I have tested and I have tested many.

               

              My only problem is in detecting the interlink and is the only problem I haven't been able to figure out so if you're giving me links for various CPU specs you're not telling me anything useful or useable.

               

              I'm looking for a way to detect the 3 interlink frequencies.

               

              The issue I see is that when I look at available docs like the http://download.intel.com/embedded/processor/datasheet/323317.pdf (section 3.6.5) I see that the FREQ register is at D0h however when I scan through this document it also uses this offset for other purposes so I have no clue how to get it to tell me the frequency information I'm looking for and the intel docs are pretty useless as far as example code is concerned.

               

              What further complicates matters is that there isn't example code I'm able to locate to show how to retrieve the information from device 8 function 2 and how to discern the frequency based on the installed CPU.

               

              I have not found any working registers that hide/unhide device 8 function 2 so this secret is the problem that prevents reading the FREQ register when it always returns 0 even after I unhide it.

               

              Here's some code but it doesn't work properly, it will unhide the QPI registers but it doesn't give you the frequency.

               

              #define INTEL_X58_55x0_QPIFREQ_REG          0xD0
              #define INTEL_X58_55x0_QPIFREQ               0x7E

               

              #define INTEL_X58_55x0_DEVHIDE1_REG          0xF0
              #define INTEL_X58_55x0_DEVHIDE2_REG          0xF8

               

              #define INTEL_X58_55x0_HIDE_DEV8_FUN2     (1 << 5)
              #define INTEL_X58_55x0_HIDE_DEV17_FUN0     (1 << 28)
              #define INTEL_X58_55x0_HIDE_DEV17_FUN1     (1 << 29)

               

              void show_intel_qpi_conf_registers(pci_dt_t *dev)
              {
              uint32_t pci_config_word;
              uint32_t     dev_addr = dev->dev.addr;

               

              pci_config_word = pci_config_read32(dev_addr, INTEL_X58_55x0_DEVHIDE1_REG);
              pci_config_word &= -(INTEL_X58_55x0_HIDE_DEV17_FUN0|INTEL_X58_55x0_HIDE_DEV17_FUN1);

               

              pci_config_write32(dev_addr, INTEL_X58_55x0_DEVHIDE1_REG, pci_config_word);

               

              }

               

              uint32_t read_qpi_freq_register(pci_dt_t *dev)
              {
              uint32_t pci_config_word;
              uint32_t     dev_addr = dev->dev.addr;

               

              pci_config_word = pci_config_read32(dev_addr, INTEL_X58_55x0_DEVHIDE2_REG);
              pci_config_word &= -(INTEL_X58_55x0_HIDE_DEV8_FUN2);

               

              pci_config_write32(dev_addr, INTEL_X58_55x0_DEVHIDE2_REG, pci_config_word);

               

              interconnect_speed = pci_config_read32(dev_addr, INTEL_X58_55x0_QPIFREQ_REG);
              interconnect_speed &= INTEL_X58_55x0_QPIFREQ;

               

              return interconnect_speed;
              }
              • 4. Re: QPI register information
                Doc_SilverCreek

                ahhhh code!!

                When it comes to coding I run the other way!!

                But the software forum may be able to help.

                 

                 

                Since all devices on the QPI bus run at the same speed, the chipset spec. should help you.

                http://www.intel.com/Assets/PDF/datasheet/321328.pdf

                 

                This spec list on pg 366-367 the QPIFREQSEL as the regester in Device 20d, function 2d offset 0Dh  

                A quick check on my system appears to be reporting the link correctly

                 

                qpi_space.bmp

                 

                I believe what your tryng to hide / unhide are internal chip links between devices within the silicon.

                 

                Good luck with your code.

                • 5. Re: QPI register information
                  websrvr

                  Your CPU has an interlink speed of 6.4GT/s and this is reflected in the register however at the time this information is required there is no OS loaded so just seeing the information without knowing how to make it viewable is the problem.

                   

                  I also don't see a software forum as navigation around this place was not considered a priority in the site design.

                   

                  Giving me the 321328.pdf file has now introduced major confusion, there is now a conflict with the device and function of the FREQ registers and the suggestion that DEV20 FUNC2 will provide the configured interlink is of no help since it does not appear to have a bit to unhide DEV20 FUN2 so you can read the registers.

                   

                  I think I can figure out how to unhide DEV14 FUNC2 so the information can be read and since anyone who has already figured it out hasn't chimed in I'm guessing it's a secret they want kept.

                  • 6. Re: QPI register information
                    Doc_SilverCreek

                    Sorry the info was not helpful.

                     

                    Maybe some one else out there who is a programmer will chime in

                    Here is a link to the software development forum  http://software.intel.com/en-us/articles/intel-software-developer-support/

                     

                     

                    I am confused about the unhide / hide part.

                    This is a standard PCI config register.

                    It is not a hidden register.

                     

                    Like you said, it can be done. I have tools for Windows, DOS, EFI and Linux to read config registers, but not being a programmer I could not say how the programming of these tools is done.

                    • 7. Re: QPI register information
                      websrvr

                      The software forum is pretty useless from a programming perspective, very little programming resources and assistance from intel requires payment.

                       

                      Tools are useless because the information is required before any OS loads so the method of reading the register is the only solution and I've only found one person doing it and they wont share the solution.

                       

                      Basically from what I can tell, DEV20 FUNC2 should have the information and by locating the device by it's PCI ID's (8086,3423) and using it's address to read the register (offset D0) I should be able to get this information however it's always 0 so some kind of action must occur first to read it, I do unhide all DEV's I need to get information from and I can see them so I know the code I am using works for unhiding.

                       

                      A hidden devise is not accessible or viewable on the bus, I have confirmed with lspci that a hidden device cannot be found so it must be unhidden before it can be accessed and this is not a hidden register but the device itself.

                      • 8. Re: QPI register information
                        Doc_SilverCreek

                        For the 5500 chipset, device 20d function 02d offset D0h is viewable with lapci which is the linux tool i use when debugging in linux.

                        If you are using a different chipset, it may have a different device, function and offset, but the same MISC regesters should be present.

                         

                        Message was edited by: Doc_SilverCreek

                        Check the x58 chip set and the device, function and offset are the same.

                        Any chance your system is running at 4.8 GT/S?

                        • 9. Re: QPI register information
                          websrvr

                          I have it working now, seems after enabling the (any) device from it's hidden state requires a reset and then the registers can be read.