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The X25-E controller has 10 channels to 10 independent NAND chips so I would assume 10.
Would it not depend on queue depth? Performance scaling stops after QD32.
If we are talking about concurrent as in how many operations can be performed in a clock cycle... I would guess 10 possible operations possible. If using toggle or double data rate NAND, it would be 20 possible operations in a clock cycle. This is my guessing based on what is public about the drive and assuming the clock is synchronous.
I guess it depends on how the question is framed.... Like how many IOPs do SSDs achieve in sequential reads at different QDs? That would be a different answer...