0 Replies Latest reply on Feb 10, 2011 1:52 PM by jannis2

    Enabling EIST (Enhanced SpeedStep) via MISC_ENABLE

    jannis2

      Hello,

       

      I bought an Intel SS4200-EHW and replaced the default Celeron 420 with a Core 2 Duo E4500. The OS is Linux 2.6.37. Everything works just fine but EIST since the BIOS does not support it (I didn't replace the CPU to have more power but to save energy since it supports EIST). I added all the information needed for cpufreq and the acpi-cpufreq driver to work to the system's DSDT and the P-states of the processor are detected just fine. The ondemand-governor tries to switch to another P-state but the processor doesn't follow. I found out that EIST is disabled via the MISC_ENABLE MSR (model specific register). Bit 16 should be set to one but it is zero. I tried to set it to 1 via wrmsr (which throws no error). When I read it back, it is still set to zero. Doing the same via kernel code during bootup has the same effect. Can the BIOS filter access to the MSRs? Is there a way to go around this or does anyone have any information about the BIOS used in the SS4200? Maybe an update/beta version is somewhere out there?

       

      More information about my tries can be found here: http://forums.gentoo.org/viewtopic-t-862889.html

       

      Best regards