1 Reply Latest reply on Apr 21, 2011 9:25 AM by

    Intel's mixup with PCIe 1.1 and PCIe 2.0  ?

    NickX

      Hi Everyone,

       

       

      While browsing datasheets today on the newish i5 chipsets, I came across the 3400series chipset. ( http://www.intel.com/Assets/PDF/datasheet/322169.pdf )

       

      On Page 44 I noticed this paragraph:

       

       

      PCI Express* Interface
      The PCH provides up to 8 PCI Express Root Ports, supporting the PCI Express Base
      Specification, Revision 2.0. Each Root Port supports 2.5 Gb/s bandwidth in each
      direction (5 Gb/s concurrent). PCI Express Root Ports 1-4 and Ports 5–8 can be
      independently configured as four x1s, two x2s, one x2 and 2 x1s, or one x4 port
      widths.

       

       

      I thought....strange? Revision 2.0?

       

      Because earlier I was reading page 49 of the Intel 82801 ( http://www.intel.com/Assets/PDF/datasheet/313056.pdf )

       

      and saw this paragraph:

       

      PCI Express* Interface

      The ICH8 provides up to 6 PCI Express Root Ports, supporting the PCI Express Base

      Specification, Revision 1.1. Each Root Port supports 2.5 Gb/s bandwidth in each

      direction (5 Gb/s concurrent). PCI Express Root Ports 1–4 can be statically configured

      as four x1 Ports or ganged together to form one x4 port. Ports 5 and 6 can only be used

      as two x1 ports. On Mobile platforms, PCI Express Ports 1–4 can also be configured as

      one x2 port (using ports 1 and 2) with ports 3 and 4 configured as x1 ports.

       

       

      After reading some comments on the Wikipedia page for PCIe about Intel and PCIe 2.0, and some sort of confusion that happened......I was completely lost as to which information was correct.

       

       

      With the i5 chipset - shouldn't the bandwidth of PCIe 2.0 be double that of PCIe 1.1??

      Which data here is correct? Where is the typo?

       

       

       

      cheers

       

       

      Nick