Hi, I am Ghanashyam and am interested in the DP55wg chipset from Intel. I am planning to use up the PCIE slots provided in this chipset and I have few questions regarding the same.
The chipset says that it provides the following PCIE slots
1. One primary x16 PCIE v2.0 slot
2. One x8 PCIE 2.0 slot with is bifurcated from the primary x16 PCIE slot
3. Two PCIE v2.0 x4 slots
4. One PCIE v2.0 x2 slot
When you say bifurcated from the primary x16, does that mean that I cannot use a x16 and an x6 card on these two slots simulataneously?
Normally PCIE endpoints are connected to the root complex via a 1: many arbitration switch ? Can i get more information on what are the path of these end points to the root complex. Are all these endpoints connected to the root complex via the switch or is the 16x endpoint directly connected to the root complex and all the others connected via the switch.
According to me if the endpoints are connecting via a switch then the bandwidth is effectively a shared bandwidth. Can you shed some light the configuration of this PCIE switch fabric for this particular chipset?