Yes, I guess it is.
However, it does not have any progress yet. T_T
There was an early internal attempt to port PAPI to the SCC. But there were not enough internal resources to continue this effort. It involves rebulding the SCC Linux kernel. One needs to go back to the PAPI archives for the last version which supported P54C and the SCC Linux version. We unfortunately have no plans to continue the effort, but it's an interesting and useful project and should work.
I made few tryes in using the performance counters and they seem to work as other intel performance counters.
To access it you need to write and read in the machine specific registers that control the performance counters.
If you are using the linux kernel, you can create a new kernel device that does it for you, or I believe you can do it also from user space.
If instead you are using a baremetal application, you need to instrument it in order to access the msr of each core.
Yes, I tried to use MSRs with RDMSR and WRMSR.
I saw the documents in this community, which has 0xC1 and 0xC2 for performance counter and 0x186 and 0x187 for Event selection register.
Is this right?
I tried to write 0x186 with WRMSR but I got an exception.
Could you tell me the address of MSR and how you do it with simple code?
I believe you are wronging the address of the registers.
If you look in section 26 (Performance Monitoring) of P54C_Architecture_And_Programming_Vol3.pdf you can see the registers adddress in table 26-1. (pp. 26-2, 26-3). It says 0x10 for TSC, 0x11 for control and event selection, 0x12 and 0x13 for the counters values.
Try with these address and see if it works.
Yes, you are right. I was looking the wrong file "Pentium_SW_Developers_Manual_Vol3_SystemProgramming.pdf".
Actually, it is little bit confusing there are two Vol3 files in the document.
Anyway, thank you for letting me using performance counters, Andrea!
Would yuo be able to share the source code you use to use performance counter?
Are you doing this in BareMetal appalications?
you can use msr-tools from http://www.kernel.org/pub/linux/utils/cpu/msr-tools/
Once built you have two binarys: wrmsr and rdmsr which enables one to read/write msr's from
userspace (but you need to be root).
./wrmsr 0x11 0x82 -> enables perfomance counter 0 to measure TLB misses
./rdmsr 0x12 -> reads events that have been captured
I knew msr-tools,
Not only you need to be root,
but I think you need to have msr kernel module available and loaded
I'll check if this is the case on SCC. (I can't access it now).
Concerning baremetal I guess I have to see msr kernel module
code in order to it.
Thank you for your answer.
Exactly what are you guys doing here?
Are you running msr on the cores? Are you building a custom Linux?
I'm very curious. We tried something like this earlier here without success, but you seem to have had early success? Can you be more specific about what you are doing? Thanks.
a little while ago I wrote a little bareMetal C/C++ environment for SCC at our university.
Thus we where able to use msr's directly.
But due to the fact that do my internship right now, this work has stalled since december.
If there is a general interest I think I would be able to provide a suitable baremetal environment
A baremetal C/C++ environment that lets you use msr ... this is a very interesting approach. Are you willing to contribute that code? Are you publishing your results anywhere?
I'm no general,
but I would definitely be interested