Your reply is, of course, encouraging but I'm not sure I know how to correctly interpret table 1-1 in section 1.2.1 of the datasheet. For the 3420 chipset, the table says that 1 or 2 DIMMs are allowed per channel and that the transfer rate for DDR3 ECC Unbuffered DIMM is "1066, 1333".
Does this mean that the processor can access BOTH modules in the same channel at either 1066 or 1333 MT/s?
How does the processor determine what transfer rate to use?
Assuming that the Xeon 3400 processor series eliminates the 1066 MT/s restriction with 2 DIMMs/ch, do you have any insight as to why the 5500 has this restriction?
The system will detrermine memory speed based on BIOS control.
Basicly if all components report that they support 1333, the system sets the clock to 1333.
If you mix any components by installing a DIMM or a processor that only supports 1066, the entire bus will clock down to 1066, so check both your memory and processor spec. before buying.
The 5500 was the first QPI processor and the processor team desided to be safe rather than sorry when it came to 2DPC loading on the memory bus.
It is again under BIOS control and you may find some vendors that desided to brave it and allowed the 5500's to clock up to 1333 2DPC.
Intel server boards follow the processor recomendation and only allow 2DPC@1333 with the 5600.