We now have a cacheable shared memory driver. Although we've only done some light testing, it appears to be working fine.
Would you like to try it out, characterize it, do some further testing and share your results with the community? We'll continue to characterize and test on this end.
Note that the there is no cache coherance among the cores. The cores do not interact through a cache-coherent shared address space; so native programming models depend on message passing or some other scheme that makes cache coherence explicit. With the SCC chip, there is no instruction that flushes the L2 cache. If you have a program that is using cacheable shared memory, you must write your own flush routine by reading in enough data to evict the data that reside in L2. We do not yet have such a routine to offer, but hope to soon.
The cacheable shared memory device is called /dev/rckdcm; dcm for definitely cacheable memory. The shared memory device that we currently have been using is /dev/rckncm; ncm for non-cacheable memory.
The SCC Linux with the cacheable shared memory driver is available for download at http://marcbug.scc-dc.com/svn/repository/trunk/CustomSCCLinux/ and is called rcklinux_dcm_03dec_1102.obj. This SCC Linux is similar to the default SCC Linux. The changes are in the following files.
You can check out the code and build your own SCC Linux. The directions are in the file "How to Build SCC Linux."