Thanks for fast replying
I read where you inform me, but I have some curiosity.
In Table 6 of EAS, the description is little bit confused.
If I write bit 1(INTR) of core configuration registers, then maskable interrupt is generated?
It could be, but in another thought, it could just enable maskable interrupt.
Then, if one of makable interrupts is generated by hardware or software, then an interrupt signal occurs.
I'm not sure about it, please just make sure that if I write INTR then maskable interrupt is generated.
I do believe that setting INTR on Pentium P54C does actually generate the interrupt. I haven't personally tried it out, but if If you are concerned, it's best for you to try it and see what happens. If you do, please post your results here.
I don't know the nature of your research, but admittedly I'm curious about why you would want to do this .. that is, have some cores generating interrupts on other cores.
Yes, that bit controls generating, not enabling the interrupt. In table 6 "active" and "inactive" refer to the signal, not enabling.
For an example of signaling another core see: