4 Replies Latest reply on Jul 28, 2014 11:37 PM by HsinChih.Lin

    Intel Verilog-A FASE SATA model issue

    maxstringer

      Hello,

       

      I am having difficulties with the Intel Verilog-A FASE model for SATA SI signal-integrity modeling. Does anybody know how to use the FASE model or convert it into an IBIS or HSPICE. What software will open this model ?

       

      I am unable to locate any documentation on Verilog-A FASE  driver-buffer models, can someone point me in the right direction.

       

      Thanks in advance.

       

      Max Stringer.