1 Reply Latest reply on Oct 25, 2010 6:06 PM by tedk

    How to clock down the memory controller?

    alexeypa

      Currently we use Tile533_Mesh800_DDR800 configuration. What is the best way to clock the frequency of the memory controllers down? We want to emulate faster cores but increasing frequency of the cores cause stability issues.

        • 1. Re: How to clock down the memory controller?
          tedk

          You can change the frequency at which the memory controllers run by creating new rlb files. These files are in  /opt/sccKit/current/settings on the MCPC. When you issue the command sccBmc -i, you are presented with the following choices:

           

          Please select from the following possibilities:
          INFO: (0) Tile533_Mesh800_DDR800
          INFO: (1) Tile800_Mesh1600_DDR1066
          INFO: (2) Tile800_Mesh1600_DDR800
          INFO: (3) Tile800_Mesh800_DDR1066
          INFO: (4) Tile800_Mesh800_DDR800
          INFO: (others) Abort!

           

          The memory controller frequency is 1/2 the number after DDR ... because of the double data rate. So to drop the memory controller frequency to 200MHz, you would need a entry like Tile533_Mesh800_DDR400. To get such an entry you have to add two files to the directory /opt/sccKit/current/settings. These two files would be Tile533_Mesh800_DDR400_preset.rlb and Tile533_Mesh800_DDR400_setting.rlb. The files are text files that contain JTAG commands.You can look inside the existing files to get an idea of how you might construct such files.

           

          You would then train the SCC system and select the new entry that appears. If the training is successful, the memory controllers are running at the new frequency. Note that running the memory controllers at 200MHz is running them below their specification. We have tried this with two internal systems. One system refused to train, and one did train successfully. The training error that resulted was not related to the memory controllers. Most likely it was  something wrong with the SIF interface or the communication to the core.

           

          If you want more detail about how you would create the needed rlb files, please send me a private message.