1 Reply Latest reply on Jul 23, 2010 2:54 PM by Dan_O

    Intel 82945 and PCI-bus


      How access to I/O space is separated from access to memory space in PCI bus. Please explain by PCI signals and the protocol. How an Intel

      CPU like Core 2 Due mobile separates I/O space from memory space? What electrical signals are involved in this process?

      When accessing I/O space, is BE#[3::0] signals of PCI protocol(byte enables) are used in PCI protocol like memory access?