1 Reply Latest reply on Aug 23, 2018 2:00 PM by Intel Corporation

    Resolving DSP Register Packing Failures

    btine

      Hi,

       

      I want to accelerate the following fixed-point operation using the fixed-point DSP multipliers on my Arria 10 board.

       

      c = ax * ay + bx * by

       

      I'm not able to fully utilize the available DSPs, even after adding enough buffering on all my operands  (see FIT report below).

      The reported reason why the packing is failing is because of "Inverted" and "Vcc", what do they mean?

      What's the recommend coding technique to fully utilize all DSPs, preventing register packing?

       

      thanks,

      -Blaise

      +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

      ; Fixed Point DSP Register Packing Details                                                                                                                                                                                                                                                             ;

      +-----------+------------------+----------------------+-------------------------------------+--------------+------------+----+--------------+------------+----+--------------+-----------------+--------------+----------------+-------------------+-------------------------+-------------------------+

      ; Name      ; Mode             ; Register Usage       ; Reasons Preventing Register Packing ; AX/CoefSelA  ; AY/ScanIn  ; AZ ; BX/CoefSelB  ; BY/ScanIn  ; BZ ; Pipeline     ; Output Register ; Uses Scan-In ; Uses Pre-Adder ; Uses Coefficients ; Uses Output Adder Chain ; Uses Output Accumulator ;

      +-----------+------------------+----------------------+-------------------------------------+--------------+------------+----+--------------+------------+----+--------------+-----------------+--------------+----------------+-------------------+-------------------------+-------------------------+

      ; add_44~12 ; Sum of two 18x18 ; partially registered ; Inverted                            ; unregistered ; registered ; -- ; registered   ; registered ; -- ; unregistered ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_45~12 ; Sum of two 18x18 ; partially registered ; Inverted                            ; unregistered ; registered ; -- ; registered   ; registered ; -- ; unregistered ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_46~12 ; Sum of two 18x18 ; partially registered ; Inverted, Vcc                       ; unregistered ; registered ; -- ; unregistered ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_47~12 ; Sum of two 18x18 ; partially registered ; Inverted, Vcc                       ; unregistered ; registered ; -- ; unregistered ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_48~12 ; Sum of two 18x18 ; partially registered ; Inverted, Vcc                       ; unregistered ; registered ; -- ; unregistered ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_49~12 ; Sum of two 18x18 ; partially registered ; Inverted, Vcc                       ; unregistered ; registered ; -- ; unregistered ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_18~12 ; Sum of two 18x18 ; fully registered     ;                                     ; registered   ; registered ; -- ; registered   ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_19~12 ; Sum of two 18x18 ; fully registered     ;                                     ; registered   ; registered ; -- ; registered   ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_20~12 ; Sum of two 18x18 ; fully registered     ;                                     ; registered   ; registered ; -- ; registered   ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_21~12 ; Sum of two 18x18 ; fully registered     ;                                     ; registered   ; registered ; -- ; registered   ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_22~12 ; Sum of two 18x18 ; fully registered     ;                                     ; registered   ; registered ; -- ; registered   ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      ; add_23~12 ; Sum of two 18x18 ; fully registered     ;                                     ; registered   ; registered ; -- ; registered   ; registered ; -- ; registered   ; registered      ; no           ; no             ; no                ; no                      ; no                      ;

      +-----------+------------------+----------------------+-------------------------------------+--------------+------------+----+--------------+------------+----+--------------+-----------------+--------------+----------------+-------------------+-------------------------+-------------------------+

      Note: Some of these fixed point DSP blocks may disappear in the final design as a result of DSP merging during placement (see the Fitter Netlist Optimizations report).