No, your processor has FOUR memory controllers.
I stand corrected (you learn something every day). ARK only identifies the number of channels, not controllers. It took some heavy digging in the datasheets to discover that there were only two controllers -- and I only discovered it indirectly via the PECI interface section ).
Ok, what I found was a field in the Device 15 Function 0 section's definition for TADWAYNESS. This is defined as follows:
channel interleave wayness
00 - interleave across 1 channel or mirror pair
01 - interleave across 2 channels or mirror pairs
10 - interleave across 3 channels
11 - interleave across 4 channels
This parameter effectively tells iMC how much to divide the system address
by when adjusting for the channel interleave. Since both channels in a pair
store every line of data, divide by 1 when interleaving across one pair and 2
when interleaving across two pairs. For HA, it tells how may channels to
distribute the read requests across. When interleaving across 1 pair, this
distributes the reads to two channels, when interleaving across 2 pairs, this
distributes the reads across 4 pairs. Writes always go to both channels in the
pair when the read target is either channel.
As I read this, I can see the answer being yes if you read it as "1 channel 'or mirror pair' " or no if you read it as "1 'channel or mirror' pair".
Yes, I am now sorry I even stepped in to try answering this...
Although I have read a number of manuals and also I have run different tests I cant find the answer in my original question.
Does anyone can help me?
I was about to move this conversation into the Server support forum, but decided not to as there is a reasonable chance of getting an answer here. I would recommend, however, that you create another copy of this query within the Server support forum, as this will improve your chances of getting a good answer. Unfortunately, while I have the ability to move a conversation, I do not have the ability to copy a conversation, so you need to do this...