3 Replies Latest reply on Sep 18, 2017 2:21 PM by Intel Corporation

    Pin delay


      I am referencing the Intel Allegro file CRB 557702_SKL_U_DDR4_RVP15_Board_Rev1_0_166_12lyr.brd for a layout I am currently working on. I have pretty much duplicated the stackup, placement and connections between the i3-6100U CPU and the two DDR4 SODIMMs. The one difference is that I have the CPU located on the bottom side of the pcb, the two SODIMMs are on the top side of pcb. On the CRB, everything is on the top. I’m wondering if that change has any effect on the pin delay values that are currently defined for each net in the CRB constraints. Does anyone know where that information comes from?