3 Replies Latest reply on Aug 14, 2017 11:21 AM by Intel Corporation

    Architecture of IMCs(Integrated Memory Controllers) in latest Intel processors

    electro_sm11

      I have been looking into Xeon architecture for a server application. I saw that Xeon supports Quad channel architecture with 3 DIMMs per channel. Following is a page from Intel's Xeon datasheet.

      • I have a doubt on the statement about DRAM controllers sharing a common address decode and DMA engine. If I have 4 cores on the Xeon processor, will I be able to access the 4 DDR channels simultaneously? For example can I use one CPU core to write to DDR channel 1 and another cpu core to read from DDR channel 2 simultaneously?
      • Also I assume the statement also means that I can have a DMA engine for a single channel at a time?

       

      Appreciate any support.