1 Reply Latest reply on May 18, 2017 5:33 PM by Intel Corporation

    GPIO Pin Status in Edison Shutdown State

    Tyler@FB

      I am running into an issue where the GPIO pins are pulling low when the Edison is powered down. I designed a circuit to drive an active low reset with an on state at approximately +4V. I level shifted and inverted the GPIO signal from the Edison (see image below). The GPIO signal is SYS_BOOT1 and refers to Edison pin GP13_PWM1.

      I designed the circuit to have a pull up resistor (R29) to turn on a NMOS-FET (T5) when the Edison is not present or shut down. The problem I'm seeing is that SYS_BOOT1 is actively being pulled to ground by the Edison. I tried lowering the pull up resistance to 1k, but that didn't solve the problem.

       

      What exactly do the Edison GPIO pins do when it is in shutdown? Am I going to have to invert my logic again to accommodate this?

       

      Thanks for the help!

        • 1. Re: GPIO Pin Status in Edison Shutdown State
          Intel Corporation
          This message was posted on behalf of Intel Corporation

          Hello Tyler@FB,

          Thank you for your interest in the Intel® Edison Breakout Board.

          The state of the GPIOs is a topic that has been discussed several times in this community, the biggest issue being the unpredictability of said pins during start up. The previous has lead to developers creating their own images to counteract the fact that the digital pins are shared by different interfaces through the multiplexing process. 

          But since your inquiry is related to the state of the GPIOs during shutdown, it seems that, as you already mentioned, inverting the logic of your design is the way to go in order to respond to the pull-down generated by the compute module.

          If you have any other question or update, don’t hesitate to contact us.

          Have a nice day.

          Regards,
          Andres V.