can anybody confirm weather MFENCE innstruction ensures committing the stores to final destination memory or it just flushes the stores out of cpu's local buffer to BIU.
Though intel software developers guide says MFENCE ensures global visibility of the preceding load/stores, but does it apply to IOMEM also.
Background : i've been writing program to calculate Latency for PIO write to PCIe based FPGA memory. my problem is how to ensure that PIO write is completed, since it is posted write.
Pseudocode is --
1) open device
2) mmap device memory to program addess space
3) clock-gettime(CLOCK_MONOTONIC, &start)
4) PIO_write to mmaped memory
5) _____________ (ensure write to destintion memory)
7) latency = end-start
I have two option for step 5)
--> either i must assert the PIO read to FPGA memory after the PIO write to make sure PIO write completed as they are processed in order.
problem with ths is, it spoils the actual latency figure as PIO read adds lots of latency (overhead of PIO read is higher than PIO write)
--> i can use MFENCE
Problem with this is , does it ensures data written to FPGA memory OR it only ensures writing is initiated (cpu handover data to TLP layer of PCIe and MFENCE returns)
is there something else available than these two. if no,which one of these is more justified for calculating high precision PIO write latency.
Any clarification is highly appreciated.
I understand you are writing a program to calculate latency for PIO write to PCIe based FPGA memory, and you are trying to find out how to ensure that PIO write is completed.
Let me apologize for any inconvenience this issue may be causing to you.
I recommend posting your inquiry on our developer’s forum so they can assist you better. This is the link to it https://software.intel.com/en-us/forum