2 Replies Latest reply on May 3, 2017 9:32 AM by Intel Corporation

    Why was the 80386 unable to execute an instruction in one cycle?


      I am writing a book about Wolfenstein 3D and the Intel 386. Looking into the cost of each 386 instructions, i noticed that none of them (including simple ADD or INC) can execute in one cycle. All of them execute in at least two cycles. I am trying to understand why.


      According to hardware reference manual of the 386, it is a pipelined three stages CPU so it should be able to execute on instruction per cycle (once the pipeline is full). Googling further, I found that the Decode Unit can only process one opcode/operand per cycle (source) so that would explain why the pipeline gets stalled.


      But if my theory is right, that call for the question: With all the design going into the 386 and the three stage pipeline, why not design the Decode Unit to be able to decode a full instruction in one cycle? That would have doubled the performance of the CPU.