We are finishing up our custom debugger for Quark D1000. Unfortunately, we cannot use OpenOCD in our application.
We have a few quick questions, to fill in missing details (not in the online documentation).
What is the maximum JTAG clock speed of the Quark D1000?
ISS 2015's aura_ftdi.cfg file uses 200KHz and indicates that up to 250KHz is safe. But so far in our experiments 249KHz is the maximum that has worked for us, and anything above 236KHz seems to only work intermittently).
We want to make sure we get good performance--but also need to ensure that we have a safe margin.
On the CRB-rev.0c board (D1000-CRB-rev.0c), what is the FTDI pinout?
Is the pinout used on D1000-CRB-rev.0c the same as the larger D1000 CRB board (e.g. DBUS4 = FTD_nRESET; DBUS6 = SECUR; DBUS7 = TRST)?
Is there a schematic (or at least a quick pinout) available for CRB-rev.0c?
We have the schematic for D1003 and D1006, but have not found a schematic online for CRB-rev.0c.
This chip is so very very cool. Thanks for making this "simplified IA32" chip available, Intel engineers.
Thanks for reaching out.
We will investigate about your questions, and we will contact you as soon as we have information.
Thank you for your patience.