3 Replies Latest reply on Apr 12, 2017 9:07 AM by aleesi

    PVP clock control

    Kaveena

      Hello,

       

      Are CCU_PVP_PCLK_DIV and pvp_clk_en accessible to developers? Figure 7 Clocking in Detail from Intel Quark SE Microcontroller C1000 Datasheet February 2017 (Document Number 334712-005EN) shows that these are present on the Quark SE C1000 to control the pvp_pclk, however they are referenced nowhere else in the document.

        • 1. Re: PVP clock control
          MichelleC_Intel

          Hi ,

           

          No , we do not have any SW implementation for these currently.

           

          Do you have a specific use case that you require these for ?

           

          -Michelle.

          • 2. Re: PVP clock control
            Kaveena

            Hi Michelle,


            We have been trying to quantify the power consumption and capabilities of the PME for a low power motion detector.  Full control over this peripheral would have been helpful.

            • 3. Re: PVP clock control
              aleesi

              Hi,

               

              The information you are requesting is not available in the public datasheet as we don't have software support for it. However it should be just a matter of configuring the below register accordingly. In addition to that we haven't measure the performance of PME at different CLKs.

               

               

              MEM Offset (00000000) 34h

              Size 32 bits

              Default 0000_38DDh

               

              BitsAccess TypeDefaultDescription

              16:1

              4

              RW/P3'h0

              Pattern Matching Engine

              Peripheral clock divider

              (CCU_PVP_PCLK_DIV)

              000b: divide by 1

              001b: divide by 2

              010b: divide by 4

              011b: divide by 8

              100b: divide by 16

              101b: divide by 32

              110b: divide by 64

              111b: divide by 128

              13RW/P1'b1

              Pattern Matching Engine

              Peripheral Clock Divider

              Enable

              (CCU_PVP_PCLK_DIV_EN)

              This bit must be written from

              0 -> 1 to apply the value

              12RW/P1'b1

              Pattern Matching Engine

              Peripheral Clock Enable

              (CCU_PVP_PCLK_EN)

              1b: enable

              0b: disable

               

              Regards,

              Alex