4 Replies Latest reply on Jul 29, 2010 6:23 PM by kvrrao

    Intel I7 Cache

    JoaoMOS

      I´m looking for the knowledge of cache system organization on I7 processors. If anybody can help me I should like to know:
      The type of organization of the different levels of cache, i.e., if they are associative, direct mapped or N set associative.
      The answer in clock cycles of a Cache reading. I suppose that level 1 will be read in 1 clock cycle. And what about cache Level 2 and Level 3?
      Is the memory interface which generates the Wait State if there is a cache miss on Level 1 or is Level 1 by itself?
      Are the different levels of cache inclusive or exclusive?
      The policy of writing is Write through or write back?

      Why I7 and these questions?

      I7 because it is my processor.

      These questions because I'm investigating about the logical interaction between cache and main memory and looking for the logical organisation of each one. I should like to see in a real situation the confirmation or not of my conclusions about cache memory.