1 Reply Latest reply on Feb 15, 2017 8:31 AM by Intel Corporation

    TCVIL for 80L186EC


      have a question if you could
      help me out that would be great, here it is:


      The parameter in question is
      TCVIL, see the attached spec pages


      On the tester I can see the CAS2:0
      data drive in manner that looks very similar to what is displayed in the
      waveform on page 46.  The data comes out on the AD15-AD13 pins at roughly
      the same time as the start of the first INTA low pulse, and the data stays on
      the outputs until just after the end of the second INTA low pulse, at which
      time the pins float.  I measure both TILIH and TIHIL and both are very
      close to the specified 2T and 4T respectively.  The problem with the TCVIL
      parameter can be seen by looking at the timing diagram.  TCVIL should be
      roughly equal to TILIH + TIHIL which equals 6T.  But the value Intel
      entered under the parameter is 8T.  This doesn’t make sense.  I
      suspect the 8T is an error and should be 6T, or that the timing diagram should
      show TCVIL running through the end of the second low pulse. 


      We believe the limit should
      be from 8T to 6T based on measurement and we suspect the datasheet is an error,
      is this assumption correct!


      If you could help answer this issue with the timing
      parameters that would be terrific!