1 Reply Latest reply on Mar 30, 2010 8:40 AM by chenhy

    DRAM slowdown on 3010 chipset

    ldonzis

      Hello.

       

      We've found a condition on one of our 3010-based systems such that when it is populated with 8GB of RAM, then heavily exercising main memory causes a dramatic slowdown in speed after a few seconds.  Note that if the system is populated with less than 8 ranks of memory (i.e., if we load it with 4 single sided or 2 double sided DIMMs), then the slowdown does NOT occur.

       

      We have noticed that when the slowdown occurs, bit 7 becomes set in the MCH ERRSTS register (i.e., value = 0080h).  If we try to clear the bit, it stays set, but if we stop exercising RAM for a moment, then we can clear the bit and it stays cleared until we begin exercising RAM again.

       

      The exercise is simple, just copying a buffer repeatedly that is larger than the L2 cache so that it's forced to go to main memory all the time.

       

      Unfortunately ERRSTS bit 7 is "reserved".  Can anyone tell us what this bit means and what might cause this?

       

      Thanks,

      lew

        • 1. Re: DRAM slowdown on 3010 chipset
          chenhy

          Hi,

           

            Intel 3010 MCH has some undocumented memory base arrdess map control register that related to the DRAM Throttling function.

           

            One is the C0DTC(Channel 0 DRAM Throttling Control) offset is 0x158h.

            Another is the C1DTC(Channel 1 DRAM Throttling Control) offset is 0x1D8h.

           

            Their Bit 21(),  Bit 17, Bit 16 are related to control the enable or disable of the (DRAM Throttling function) & (DDR2 400 or DDR2 533 DRAM Throttling) & (DDR2 667 DRAM Throttling).

           

            When DRAM Throttling function is ebabled and if dram work with single channel mode or full channel are populated drams configuration,

            in our experiments we found the DRAM Throttling function began to work and saw the memory performance will go slow down and ERRSTS bit 7 will be   assreted also.

           

            So if we manually to disable the Bit 21 & Bit 17 & Bit 16 of the Channel 0 & Channel 1 DRAM Throttling control register then the memory copy performance will not go to slow down.

           

            I wrote a tool to manually disable the DRAM Throttling function under Linux call disDT.c for your verification.

           

          >>>

          /*
          Author: Lorence Chen 2010/03/30
          */

          #include <stdio.h>
          #include <fcntl.h>
          #include <string.h>
          #include <sys/vfs.h>
          #include <unistd.h>
          #include <sys/mman.h>
          #include <stdlib.h>
          #include <errno.h>

          #define u8 unsigned char
          #define u16 unsigned short
          #define u32 unsigned int

          //4.2 MCHBAR Configuration Register Details
          // The MCHBAR registers are offset from the MCHBAR base address. Table 4-2 provides an
          // address map of the registers listed by address offset in ascending order. Detailed bit
          // descriptions of the registers follow the table.
          //
          // Table 4-2. Undocumented MCHBAR Register Address Map
          // Address Offset    Register Symbol    Register Name
          //  
          // 158h              C0DTC              Channel 0 DRAM Throttling Control
          // 1D8h              C1DTC              Channel 1 DRAM Throttling Control

          #define MCHBAR_ADDR      0xFED14000
          #define MCHBAR_C0DTC     0x158
          #define MCHBAR_C1DTC     0x1D8

          #define MSM_MDP_PHYS MCHBAR_ADDR

          #define MSM_MDP_SIZE 0x00001000
          #define MSM_MDP_MASK (MSM_MDP_SIZE-1)
          int main(){

            void *vaddr1, *vaddr2;
            int errors = 0;
            int fd;

            fd = open("/dev/mem", O_RDWR | O_SYNC);
            printf("/dev/mem opened.\n");
            fflush(stdout);

            printf("MCHBAR ADDRESS is 0x%8Xh\n", MSM_MDP_PHYS & ~MSM_MDP_MASK);
            vaddr1 = mmap(0, MSM_MDP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED,\
            fd, MSM_MDP_PHYS & ~MSM_MDP_MASK);

            if(vaddr1 == (void *) -1) {
            printf("mapping error!!\n");
            return -1;
            }

          //MCHBAR_C0DTC    0x158 
            vaddr2 = vaddr1 + MCHBAR_C0DTC;
            *(volatile u32 *)(vaddr2) = 0x2300; //Here please to make sure to set Bit 21, Bit 17 & Bit 16 to value 0 to disable the DRAM Throttlink function.
            printf("MCHBAR_C0DTC (offset MCHBAR + 0x158) value is 0x%8Xh\n", *(volatile u32 *)(vaddr2));
          //MCHBAR_C1DTC    0x1D8 
            vaddr2 = vaddr1 + MCHBAR_C1DTC ;
            *(volatile u32 *)(vaddr2) = 0x2300; //Here please to make sure to set Bit 21, Bit 17 & Bit 16 to value 0 to disable the DRAM Throttlink function.
            printf("MCHBAR_C1DTC (offset MCHBAR + 0x1D8) value is 0x%8Xh\n", *(volatile u32 *)(vaddr2));                          
            fflush(stdout);
          //<<
            munmap(vaddr1, MSM_MDP_SIZE);

            close(fd);
            return errors;
          }

          <<<

           

          to compile it please use command:

          gcc -O2 -o disDT disDT.c

          to run it please use

          ./disDT

          before you run the combo.c

           

          please check it.

           

          Lorence

          2010/03/30