Preliminary review, need verification from Intel. Why is the value 1.8v on J12 pin 27 when the level translator should be 3.3V n this pin.
Tuchuck dev board
J12 pin 27: ISH_GPIO 4 LS
Level converter EU18 translates bidirectionally "ISH GPIO 4" pin 4 - "ISH GPIO 4 LS" pin 17
I am also always reading 1.8V for J12 pin 27
Even when the bit is successfully cleared, and verified with read() as "zero" value
root@intel-corei7-64:~# mraa-gpio list
01 GPIO: GPIO
02 SPP1RX: GPIO SPI
04 SPP1TX: GPIO SPI
05 19.2mhz: GPIO
06 SPP1FS0: GPIO SPI
07 UART0TX: UART
08 SPP1FS2: GPIO SPI
10 SPP1CLK: GPIO SPI
11 I2C0SDA: I2C
12 I2S1SDI: GPIO
13 I2C0SCL: I2C
14 I2S1SDO: GPIO
15 I2C1SDA: I2C
16 I2S1WS: GPIO
17 I2C1SCL: I2C
18 I2S1CLK: GPIO
19 I2C2SDA: I2C
20 I2S1MCL: GPIO
21 I2C2SCL: I2C
22 UART1TX: UART
24 UART1RX: UART
26 PWM0: GPIO PWM
27 I2S4BLK: GPIO
28 PWM1: GPIO PWM
30 PWM2: GPIO PWM
32 PWM3: GPIO PWM
35 I2S4BLK: GPIO
Thanks for contacting us.
I appreciate all the information provided. I have tested ISH_GPIO pins and I have got the same results you have mentioned. However looking at the Mraa documentation I believe those pins are occupied in other functions, and for that reason we are not able to use them. Please take a look at the Mraa Pin Mapping for that information.
Hope this information helps.
Please provide some additional insight into investigating this issue, which would be greatly appreciated.
Your answer appears vague, and minimalistic.
You also did not answer the question regarding the voltage translation values. Please read the information carefully in the future. Thanks in advance.
The pin mapping for mraa states: 27 I2S4BLK: GPIO
which means that the pin is configurable as a GPIO, correct? Is there another document you are aware of which states otherwise?
If this is not the case, please state which document, or additionl information, states that other "specific" functions do not allow this pin to be used as a GPIO.
If this pin is being used for another function, then that function should be capable of being inhibited, and GPIO config and setup for the pin, as an output should work fine, tested, documented to allow others to perform this operation.
it has been a while, no status?
We are integrating SPI with OSTRO, and Ubuntu Core, and OSTRO readings for SSP1_FS0 Chip select are 1.8v. This output pin should be 3.3volts!
The Tuchuck board has 1.8v to 3.3v "level shifters" (LSF0108RKSR -bidirectional), why are we reading 1.8 volts instead of 3.3 volts?
Schematics for Tuchuck pullup "EN", as required.
VREF_B when measured is 2.6v, should be 3.3v
does the BIOS control the VSYS voltage levl, or is there an API to set the VSYS?
Are we on the threshold for:
Vref_B reference voltage (B) Vref_A + 0.8 5.5 V
2.6v measured for VrefB. Why was 2.6 Volts selected for VRefB?
VrefA 1.8v + 0.8v = 2.6v!!! No margin! What happens if minimum voltage is not provided, does the system fall back to VrefA?
13 SPI interface
The Intel Joule expansion board routes two SPI interfaces from the module, through a level translator to convert the module 1.8 V logic levels to those required by the breakout board. The breakout board should include appropriate pullup values to the desired voltage, but not to exceed 3.3 V.
- 13.1 SPI level transitions
All of the SPI interface lines are level transitioned (shifted) between the breakout connector 3.3 VDC levels and the Intel Joule compute module, which operates at 1.8 VDC levels.
Level translation is performed by a Texas Instruments* LSF0108RKSR open drain translator.
The expansion board uses a 200 kΩ pullup resistor from the +V3P3V supply to enable EU17 when the expansion board is active.
Please re-direct to the hardware and embedded experts at Intel, and answer ASAP.
Thank you for all the details provided, we would like to let you know that we are still investigating regarding why we are getting 1.8V instead of 3.3V as well as in your other case: Need mrra SPI CS ("Chip Select") configured to "active high", so as soon as we have useful information we’ll let you know.
we would like to update this case regarding changing the ISH_GPIO_0 ~ 6 values, we have updated the Mraa library version to Version v1.5.1-24-g2ea6810 on Intel GT Tuchuck, and we didn't have any issues changing the GPIO value, here you can find how to update the library: Installing and updating middleware libraries and you can use this command to get the Mraa version: mraa-gpio version.
Hope this information helps.
ningxin.hu, And Yermi
I have tested ISH-_IO0 thru ISH_IO6, and they appear to be controllable using mraa-gpio set [pin] [lvl] successfully, using the latest version of mraa. Thanks for the update.
1) There are still a number of other GPIO pins which fail. Can you verify all of them, and fix the ones that do not work? Do you need a list?
2) Also the syntax/naming convention for using mraa-gpio list does not match the mraa: Intel Joule pin labels (mraa: Intel Joule)
For Example: Pin 26 ISH_IO5: GPIO is I2S4SDI
3) the SPI0 Clock (SPICLKB) appears to be located on J13.25, which is labelled SPP0FS3: GPIO SPI?
Thanks for your patience, we would like to let you know that ISH_GPIO signals require pull-up resistors on the 3.3V side of the level shifter to achieve the target level. This is required due to the open-drain nature of the level-shifter design. The information for pull-ups is provided in the Joule Expansion Board Hardware Guide in section 10: http://www.intel.com/content/www/us/en/support/boards-and-kits/intel-joule-kits/000023394.html.
Additionally, we would suggest you to open a new thread in case you have additional questions. Also, please open another one in order to help you with your last questions, if it is possible, post a list with the GPIO pins that fail.
Hope this information helps,