1 2 Previous Next 19 Replies Latest reply on Jan 15, 2017 10:18 PM by Aravind@ar

    Spread Spectrum clock

    Aravind@ar

      Hello There,

       

      How do I disable Spread Spectrum clock in intel galileo board ?

       

      Thanks & Regards,

      Aravind.

        • 1. Re: Spread Spectrum clock
          FGT

          Aravind@ar wrote:

           

          Hello There,

           

          How do I disable Spread Spectrum clock in intel galileo board ?

           

          Thanks & Regards,

          Aravind.

          Hi Aravind,

           

          I'm curious, what is the "Spread Spectrum clock"? what is it used for?

           

          (I've taken at look at Datasheet for Intel® Galileo Board and I did not find any information about it).

           

          Fernando.

          • 2. Re: Spread Spectrum clock
            Intel Corporation
            This message was posted on behalf of Intel Corporation

            Hello Aravind@ar,
             
            Thanks for reaching out!
             
            Do you have any updates about this?
             
            I'd like to insist on Fernando's question, could you please let us know what you mean by Galileo's Spread Spectrum clock? Also, if you could please let us know a little bit more about your project we might be able to help you more accurately.
             
            We'll be waiting for your response.
            -Peter.

            • 3. Re: Spread Spectrum clock
              Aravind@ar

              Hello Peter,

               

              Thank you for response.  Sorry for being late on this.  We have PCI Bridge connected to Root Port 0 of Quark Soc 1000.

              We want to disable the SSC [ Spread Spectrum Clock] for  PCI root port 0.  Yes the original Quark Soc Data Sheet is not having

              any reference to "SSC". However there is Quark Spec Update published Feb 2015

              ------------------------

              Intel® Quark™ SoC X1000

              Specification Update

              February 2015

               

              February 2015 Specification Update

              Document Number: 329677 Revision: 006

              ----------------

              From Spec update above in  Page 37, SSCCTL [Spread Spectrum Clocking Control (SSCCTL): 0x14 Target ID: 0x03 ] is defined.

              Details below from the Spec update to Quark Soc 1000..  [ I do not have link to document and hence details below ]

              =================================================================

              Register Missing from Section 14.5 PCI Configuration Registers

              Issue: Spread Spectrum Clocking Control (SSCCTL) register is missing from the Intel®

              Quark™ SoC X1000 Datasheet.

              New Text: Added Section 15.5.54 Spread Spectrum Clocking Control (SSCCTL)

              14.5.54 Spread Spectrum Clocking Control (SSCCTL): 0x14 Target ID: 0x03

              Register Offset : 0x14

              Access : R/W; RO

              Size : 32 bits

              Register Default: 0000_0000_0000_0000_0000_0000_0000_0000

              Affected Docs:Intel® Quark™ SoC X1000 Datasheet

              Bit

              Range Access Default Fuse

              Ovrd Description

              31:12 RO 00000h no Reserved: Reserved

              11:8 R/W 0h no Reserved: Engineering Reserved

              7:4 RO 0h no Reserved: Reserved

              3 R/W 0b no

              SSC Pattern Halt: Halt generation of the SSC Pattern. Software sets this register field

              and waits for at least 32us to allow pattern to finish up its current modulated clock period and

              set SSC phase offset back to 0. After this point, software may make update to these register

              fields: SSC Max Phase Step, SSC Phase Increment Value, SSC Pattern Repeat Counts, SSC

              Spread Mode. Then software clear this register field to restart the hardware SCC pattern.

              1: Halt generation of SSC; 0: Allow SSC generation to continually run

              2:1 R/W 00b no

              SSC Spread Mode: Select the spread mode.

              00: Down spread; 01: Center spread; 10: Up spread (RSVD); 11: RSVD

              Note: SSC Pattern Halt must be asserted before this control can be

              changed.

              0 R/W 0b no

              SSC enabled: The bit determines whether the entire SSC block is enabled (0) or disabled

              (1). When the disabled state is entered all components of the SSC will be shutdown, with the

              exception of logic operating in the CRA domain (I.e. config access). The disable state will

              only be active when the SSC Reset FSM is in S7 or S0. If this signal becomes a 1 when in S7,

              ------------------

               

              So using the above register SSC can be disabled.  However looking at the EDK2 code base, at link https://github.com/tianocore/edk2

              I was not sure where to modify the code ?  I want to make use of the SSCCTL feature.

               

               

              regards

              • 4. Re: Spread Spectrum clock
                Intel Corporation
                This message was posted on behalf of Intel Corporation

                Hi Aravind@ar,

                In case you are wondering the document can be found here: http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-spec-update.html.

                Thank you for clearing up your doubt, it is now clear to me. Please let me investigate about this and if I'm able to find something useful for you I will make sure to share it with you.

                -Peter.

                • 5. Re: Spread Spectrum clock
                  Aravind@ar

                  Hi Peter,

                   

                  I am trying to access this SSCCTL register in EDK2 code base, but the offset that is mentioned in quark-x1000-spec-update is in conflict according to  PCIe standard for type-1 header (root port).

                   

                  SSCCTL - offset - 0x14 , but according to PCIE the first 256 bytes are standard configuration registers.

                  http://wiki.osdev.org/PCI#Configuration_Space

                  http://wiki.osdev.org/PCI_Express

                   

                  Also the register description says Spread Spectrum Clocking Control (SSCCTL): 0x14 Target ID: 0x03,  what is this Target ID - 0x03 ?

                   

                  Thanks & Regards,

                  Aravind.

                  • 6. Re: Spread Spectrum clock
                    Intel Corporation
                    This message was posted on behalf of Intel Corporation

                    Hi Aravind,

                    I understand let me try to see what this means. I'll try to get back to you as soon as possible.

                    -Peter.

                    • 7. Re: Spread Spectrum clock
                      Intel Corporation
                      This message was posted on behalf of Intel Corporation

                      Hi Aravind,

                      The information about how to enable SSCCTL is located in the document CDI#554070Intel Quark SoC X1000 Family Test and Compliance Tools Guide Rev 0.9, which is available to customers that have an NDA with Intel. The information can be found under chapter 4, and I am able to provide you with the following snippet:
                       
                      How to control SSC in PCI-E
                       
                      1.) To control SSC in PCI-E and test it functionality, you may refer to the Intel Quark SoC X1000 Family Test and Compliance Tools Guide Rev 0.9 as below:
                      http://www.intel.com/cd/edesign/library/asmo-na/eng/554070.htm
                       
                      2.) To check SSC is enable or disable:
                      Clocking – SSC is enabled by default.
                       
                      In the file QuarkSocPkg\QuarkNorthCluster\Include\QuarkNcSocId.h, add the following
                      define line:
                      #define QUARK_ICLK_SSC0 0x0214
                      In the file QuarkSocPkg\QuarkNorthCluster\Library\IntelQNCLib\IntelQNCLib.c, add
                      the following code to the function PeiQNCPreMemInit in order to disable SSC:
                      QncIClkOr (
                      QUARK_ICLK_SSC0,
                      BIT0 // bit[0] set
                      );
                       
                      Make these changes and re-build the EDK Image.

                      I hope this information helps you.
                      -Peter.

                      • 8. Re: Spread Spectrum clock
                        Aravind@ar

                        Hello Peter,

                         

                        Thank you for your response.

                         

                        I made the changes that you have suggested in EDK2 source code and rebuilt the image. But when i boot it, the bios hangs. Please find the below log.

                         

                        Also the link (http://www.intel.com/cd/edesign/library/asmo-na/eng/554070.htm) that you have provide me is not accessible by me.

                         

                        MtrrSetMemoryAttribute() WB:00000000FF800000-0000000000800000

                          Status = Success

                        MTRR Settings

                        =============

                        MTRR Default Type: 0000000000000C00

                        Fixed MTRR[00]   : 0000000000000000

                        Fixed MTRR[01]   : 0000000000000000

                        Fixed MTRR[02]   : 0000000000000000

                        Fixed MTRR[03]   : 0000000000000000

                        Fixed MTRR[04]   : 0000000000000000

                        Fixed MTRR[05]   : 0000000000000000

                        Fixed MTRR[06]   : 0000000000000000

                        Fixed MTRR[07]   : 0000000000000000

                        Fixed MTRR[08]   : 0000000000000000

                        Fixed MTRR[09]   : 0000000000000000

                        Fixed MTRR[10]   : 0000000000000000

                        Variable MTRR[00]: Base=00000000FF800006 Mask=00000000FF800800

                        Variable MTRR[01]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[02]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[03]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[04]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[05]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[06]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[07]: Base=0000000000000000 Mask=0000000000000000

                         

                        MTRR Ranges

                        ====================================

                        UC:0000000000000000-00000000000FFFFF

                        UC:0000000000100000-00000000FF7FFFFF

                        WB:00000000FF800000-00000000FFFFFFFF

                         

                        MtrrSetMemoryAttribute() WB:0000000080000000-0000000000080000

                          Status = Success

                        MTRR Settings

                        =============

                        MTRR Default Type: 0000000000000C00

                        Fixed MTRR[00]   : 0000000000000000

                        Fixed MTRR[01]   : 0000000000000000

                        Fixed MTRR[02]   : 0000000000000000

                        Fixed MTRR[03]   : 0000000000000000

                        Fixed MTRR[04]   : 0000000000000000

                        Fixed MTRR[05]   : 0000000000000000

                        Fixed MTRR[06]   : 0000000000000000

                        Fixed MTRR[07]   : 0000000000000000

                        Fixed MTRR[08]   : 0000000000000000

                        Fixed MTRR[09]   : 0000000000000000

                        Fixed MTRR[10]   : 0000000000000000

                        Variable MTRR[00]: Base=00000000FF800006 Mask=00000000FF800800

                        Variable MTRR[01]: Base=0000000080000006 Mask=00000000FFF80800

                        Variable MTRR[02]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[03]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[04]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[05]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[06]: Base=0000000000000000 Mask=0000000000000000

                        Variable MTRR[07]: Base=0000000000000000 Mask=0000000000000000

                         

                        MTRR Ranges

                        ====================================

                        UC:0000000000000000-00000000000FFFFF

                        UC:0000000000100000-000000007FFFFFFF

                        WB:0000000080000000-000000008007FFFF

                        UC:0000000080080000-00000000FF7FFFFF

                        WB:00000000FF800000-00000000FFFFFFFF

                         

                        SecStartupPhase2() Stack Base: 0x8007C000, Stack Size: 0x4000

                        Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE

                        Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3

                        Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A

                        The 0th FV start address is 0x000FFF10000, size is 0x000F0000, handle is 0x0

                        Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39

                        Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38

                        Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

                        Install PPI: CEAB683C-EC56-4A2D-A906-4053FA4E9C16

                        Install PPI: 6F8C2B35-FEF4-448D-8256-E11B19D61077

                        Evaluate PEI DEPEX for FFS(9B3ADA4F-AE56-4C24-8DEA-F03B7558AE50)

                          RESULT = TRUE (Apriori)

                        Loading PEIM at 0x000FFF1C218 EntryPoint=0x000FFF1C2F0 PcdPeim.efi

                        Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480

                        Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1

                        Install PPI: 4D8B155B-C059-4C8F-8926-06FD4331DB8A

                        Install PPI: A60C6B59-E459-425D-9C69-0BCC9CB27D81

                        Evaluate PEI DEPEX for FFS(55961E20-B0D9-4553-9948-E3ECF0BE0889)

                          RESULT = TRUE (Apriori)

                        Loading PEIM at 0x000FFF2014C EntryPoint=0x000FFF2021C PlatformConfigPei.efi

                         

                         

                        Regards,

                        Aravind.

                        • 9. Re: Spread Spectrum clock
                          Intel Corporation
                          This message was posted on behalf of Intel Corporation

                          Hi Aravind,

                          I understand, this link is also accessible under NDA.

                          Please let me analyze the data you provided me I will back to you.

                          -Peter.

                          • 10. Re: Spread Spectrum clock
                            Aravind@ar

                            Hi Peter,

                             

                            Adding some additional info

                            I have tested the bios with the suggested changes on Galileo Gen2 board which does not have any PCIE device and also on our custom board which has same SOC as Galileo Gen2 with a PCIE device attached.

                             

                            On both of these I am observing a similar behavior as shared earlier.

                             

                            Thanks & Regards,

                            Aravind.

                            • 11. Re: Spread Spectrum clock
                              Intel Corporation
                              This message was posted on behalf of Intel Corporation

                              Hi Aravind,

                              Thanks for sharing this information, it is of help. I am still investigating what might be happening, I will keep you updated.

                              -Peter.

                              • 12. Re: Spread Spectrum clock
                                Aravind@ar

                                Hello Peter,

                                 

                                Thank you for response.

                                I hope you will get a chance to analyze the debug provided and suggest a suitable working configuration for SSC disable.

                                 

                                Wishing you Happy new year 2017 ahead.

                                 

                                regards

                                • 13. Re: Spread Spectrum clock
                                  Intel Corporation
                                  This message was posted on behalf of Intel Corporation

                                  Hello Aravind,

                                  I can confirm that we have been able to replicate the system halt you saw on a Galileo Gen2. We will continue to work on this and update you as soon as we can.

                                  Happy new year to you too!
                                  -Peter.

                                  • 14. Re: Spread Spectrum clock
                                    Aravind@ar

                                    Hello Peter,

                                     

                                    Can you kindly share any update on the above issue.

                                    I hope there is no issue with the Chipset and Chipset does contain the Register to Disable SSC.

                                    I ask, as when I connect an JTAG debugger and browse I do not find Port 34 (or) Register 34 that is used to Disable SSC.

                                    The CPU / Board seems unresponsive the moment the SSC disable code is executed.

                                     

                                    regards

                                    Aravind

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