6 Replies Latest reply on Oct 14, 2016 6:51 AM by Intel Corporation

    NUC5i7: M.2 Stackup Layout


      Hello Everybody,


      I'd like to do my own M2 Card that I would connect at my M2-Socket.

      What Kind of PCB-Layout do Intel recommend ? Or what would you recommend ?


      I'd like to root the 4 PCIE-Lanes+3V3+GND+PCIE-signals (46 pins).

      The min. thickness of the m.2 module is 0.8mm.


      So it's difficult to make a 4-layer PCB.


      Thanks for your advices





        • 1. Re: NUC5i7: M.2 Stackup Layout

          Here are some comments I received from a design engineer:


          • The PCB must be the proper thickness otherwise it won't plug into the M.2 connector, so stating min = 0.8mm isn't correct; its thickness must fall within the proper min/max tolerance range for the connector.


          • The design must be 4 layer at a minimum to ensure proper ground referencing for the PCIe lanes. The high speed PCIe signals should be routed with a trace width to achieve 50Ω impedance to the reference plane and spacing for 85Ω impedance differentially. What that width and spacing needs to be is entirely dependent upon the PCB stack up and must be calculated based upon the stack up from the PCB manufacturer.


          • These rules are important for good performance, I've seen poorly routed adapter cards that down train to gen 1 speeds.


          Hope this helps,


          • 2. Re: NUC5i7: M.2 Stackup Layout
            Intel Corporation
            This message was posted by Intel Corporation on behalf of



            Please refer to the previous post, and let me know if that helps you.




            • 3. Re: NUC5i7: M.2 Stackup Layout



              Like always is Scott great with these answers.

              But to be honest, I had wished more informations. Like a typical 4-Layer PCB stackup with the corrsponding thickness" and associated ground planes

              Or something like a Design guideline.


              For example I had done something like this.



              1.Layer : Foil+plating


              2.Layer Ground


              3.Layer Ground


              4 Bottom Layer (signal)


              There is already existing PCIe-design guidelines. But it is not applied to M.2 slot. There is a lack of Information regarding this.

              There also a lot of criteria to consider like differential impedance, maximum length, L/W. Target Z


              I expected something like an application note or strong advises to do the best design.


              But I think it's ok


              Thanks Scott for the answer again





              • 4. Re: NUC5i7: M.2 Stackup Layout

                Well, being the software guy, I am not sure what else I can say. I asked the DE for comment; we'll see if he has any other Perls of Wisdom he wants to pass on. I know that the PCI SIG has a specification for M.2 available but I don't know of any other DGs or ANs (sorry).



                • 5. Re: NUC5i7: M.2 Stackup Layout

                  No Problem Scott.

                  It's ok for me.


                  Thanks a lot for what you did


                  Your answer is satisfying. And more.





                  • 6. Re: NUC5i7: M.2 Stackup Layout
                    Intel Corporation
                    This message was posted by Intel Corporation on behalf of

                    N.Scott.Pearson thank you for your help.


                    aaroni, if there is something I can help you with, let me know.