Looking at the block diagram on this page, http://ark.intel.com/Product.aspx?id=36941, it appears that 4 of the 6 cores are controlled by one Memory Controller Hub and the 2 remaining cores are controlled by another Memory Controll Hub.
Is that an accurate interpretation?
thanks in advance,
The E7xxx chips can be used in a quad socket or dual socket configutration.
The block diagram shows the quad socket linked to the MCH or the dual Socket link to MCH.
Each socket has a 6 core chip, so you have 12 or 24 cores.