5 Replies Latest reply on Oct 6, 2016 4:04 PM by Intel Corporation

    Core i7-6900K Intel 64 architecture specifics


      Hello, I'm a computer science student and I'm doing some research on the Intel Core i7-6900K processor. The thing is that I must find very specific information on this processor and its architecture. I've looked through the official Datasheets (volume 1 and 2 and the spec update) and the Intel® 64 and IA-32 Architectures Software Developer’s Manual (Volume 1, basic architecture) and so far the information found is scarce in comparison of what I still need to find. On a list, that information would be:

      • The instructions per cycle this processor is able to processes, and specifically the number of instructions per fetch, decode, issue and commit of the pipeline.
      • The size of the buffers, specifically the size of the instruction window and the Load-store queue size.
      • The bandwith and the latency to the main memory
      • The arithmetic logical units (ALUs) for the integer operations, and the ALUs for the floating point operations


      For the ALUs I found something on the Sofware Developer's Manual: "Three full arithmetic logical units", Execution Core at page 43 where I also found "Four-wide decode unit can decode 4 instructions per cycle or 5 instructions per cycle with Macrofusion", but is this information valid for the processor that I'm looking for? On the Table 2-2. Key Features of Most Recent Intel 64 Processors, the latest processor is from 2011, and I'm looking for information of a 2016 processor. Are there any other recommended documents that I might read to find some of the other information I'm looking for?


      Thank you very much for any advice or help.