Victim Caches/Pseudo Associative Caches

[GGnan]

Hello,

I would like to know about the usage(if any) of victim caches/pseudo associative caches in Intel architectures. Are there any documentations available on the same? Any pointers would be appreciated.

Thanks & Regards,

Gnanambikai

[idata]

Hello gnanukrishna,

In this case, for better support please post your question at the following link:https://software.intel.com/en-us/ https://software.intel.com/en-us/ Regards, Ivan

[AJana1]

Hello gnanukrishna,

As far as I know at this moment, Intel almost does not use victim/exclusive cache on their products, and that is the most prominent difference between Intel processors and others. Victim or exclusive cache is a backward or back-trace style cache, in other words, embracing the idea of looking back and find something that would happen again! But not all the passed things would happen again, and the actual performance for this kind of cache is not always the idealised, but comparably easier and cost effective to implement. The Smart Cache for Intel processors, since Intel Pentium Pro/II, is inclusive cache. Same shadows (cached data) might exist through all level of caches in a much more fair way, one changed, all would be further changed by the caching system itself. The last level cache for Intel processors might also play as a look-aside cache, working simultaneously with system memory system (L2 cache in P6 vs L3 cache in Core I series). The inclusive cache would also save the bandwidth of system bus, such as the L2 Cache found on Intel Core 2 processors, in which two cores share the same L2 cache. Or in other words, that L2 cache serve for two cores, working with memory system simultaneously. If hit, it would actively provide its service towards cores, and stop further retrieving data through front side bus (FSB). The victim/exclusive cache found in AMD processors act quite passive, old and stale shadow would be victim-ed out, eventually dropped or put back to system memory. Caching system is not that smart as Intel's, so even at the age of Pentium Pro. Multi processors could be connected through a single Front Side Bus which they share, but Athlon MP would need support of a switch-bridge chipset to provide each separate front side bus to work. And this switch-bridge chipset is further refined into xbar in AMD K8 and later processors. The inclusive-victim cache found on AMD 10h processors (L3 cache) is different from Intel's smart cache. Even though it is shared among cores, but victim style also plays a major role!

Best Regards,

Aaron Janagewen