7 Replies Latest reply on Nov 7, 2016 12:11 PM by Intel Corporation

    Is the Edison a good choice for sampling 6 analog microphones at 11 kHz each?


      I am working on a project that requires me to analyze data from 6 microphones at the same time. I need to sample each of them at a minimum of 11 thousand samples per second. My (C++) program will process the data in real time and search for known patterns. It is important that the microphones be very small and I am currently using ADMP401 microphone breakouts from Sparkfun. Will I be able to accomplish this with an Intel Edison?


      So far I have been testing my Intel Edison with one microphone through an MCP3002 analog-to-digital converter. It uses SPI for communication, and while I can turn up the SPI frequency well into the MHz range on the Edison, there is a delay of 220 to 240+ microseconds between the SPI clock sequences of each sample read. I am reading the ADC with spidev and the ioctl function in a loop that has nothing else in it. Because of the delay, my effective sampling rate is never better than about 4.5 kHz. I used an oscilloscope on the SPI clock line to verify that my SPI frequency was as fast and I instructed in my code, but the delay between samples is mostly in the 220 to 240 microsecond range regardless of the SPI frequency. I tried the same code (with a different device file name, of course) and sensor/ADC setup with a Raspberry Pi and noticed a 60 to 80+ microsecond inter-packet delay, which, when added to the actual SPI communication time, achieved an approximately 10 kHz sampling rate. I doubt that the delay is solely due to the processing time of the MCP3002, since its datasheet says that it can process 75,000 to 200,000 samples per second, which corresponds to a sampling interval of 5 to 13 microseconds.


      To address the SPI delay, I did some research and came upon this thread which spawned the project discussed here. If I tried to build my own kernel (am I saying that right?) for the Edison with this approach, would it lessen the inter-packet delay or just improve the clock frequency within each packet? Should I write a Linux device driver or kernel module as discussed here? I have no experience with these approaches. Are they different approaches?


      I have looked into simultaneous sampling ADC chips. I figure that since I am potentially within reach of sampling one microphone through the MCP3002 at 11 kHz, I could connect all 6 of my microphones to a simultaneous sampling ADC and focus on getting the inter-packet delay consistently under 80 microseconds.


      Another issue I face is that the delay between packets is variable. With the Edison, it is typically 220 to 240 microseconds, but often over 300. With the Pi, it is typically between 60 and 80 microseconds, but often over 100. My data processing will suffer if I can't sample the microphones at consistent intervals.


      Someone recommended using an FPGA. Is that appropriate? I am open to changing anything and everything about my approach.