Could you provide more details on how you interfaced the SoC with the DRAM? Also, you mention you’re unable to initialize the memory, can you provide the output of the halt error log?
I’ve also found some useful documents that discuss the memory controller. Check them out here:
- http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-uefi-firmware-writers-guide.html . Look at Section 5
- http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html . Look at section 13.
Our Hardware is designed with Single DDR3 chip of 512MB size and 8 bit data width interfaced to Quark SoC x1000.We are not able to find required parameters to configure the BIOS for x8 bit channel width in the provided "X1000 UEFI Firmware Writers Guide 330236_006US.pdf".
Could you please help us in providing settings for channel width to x8 instead of x16 and also the required PCD MRC parameters to build BIOS for edk2 setup.
Thank you for your quick response.
As Narendra said, we are using Single DDR3 chip of 512MB size and 8 bit data width interfaced to Quark SoC x1000 using only 8 data lines. Please find the connections in the below figure.
As per uefi firmware writers guide we have changed the following mrc parameters as follows dram_width=0(x8) rank_mask=1(rank 0 enable) chan_mask=1 channel_width=1(x16, as there is no other setting mentioned for x8) dram density=3(4Gbit)
Also find the bios log at which the system is halt
Rcvn ch0 rnk0 ln1 : pi=FFFFFFFF
RD32 012 00000070 00000900
WR32 012 00000070 00F00900
RD32 012 00000038 00000000
WR32 012 00000038 3F000000
RD32 012 0000007C 00000824
WR32 012 0000007C 00000024
CH0 RK0 BL1
Thank you for providing the BIOS log and the schematics we requested. We’ll do some research about your questions and reply to you soon.
Any update on this.
Thanks & Regards,
Thank You for your support Sergio.