4 Replies Latest reply on Aug 30, 2016 1:49 PM by wingman99

    How is  Dual Channel DDR3 routed to CPU?


      I will use XEON(R) E3-1200 v3 DRAM Controller on my desktop as an example, I am confused how Dual Channel DDR3 works.

      On page 18 "2.1 System Memory Interface" of datasheet, it says: Two channels of DDR3/DDR3L Unbuffered UDIMM with a maximum of two DIMMs per channels.

      What I learned is that DDR3 PCB Layout is using fly-by topology, so all data lines from memory ICs are directly connected to CPU, but address/cmd lines are shared by different memory ICs.

      For this XEON(R) E3-1200 v3 DRAM Controller, there are 4 memory slots on the motherboard, 2 slots for each channel. I have one memory installed for each channel, totally 2. Since each memory slot are 64-bit wide data bus, and this memory controller is also 64-bit wide, so each memory is directly connected to its own channel of XEON(R) E3-1200 v3 DRAM Controller in this configuration.

      But if I use all these 4 slots to add more memory, then for each channel, there are two memory slots connected, my questions is: are these two slots sharing same data lines on PCB? If so, then this is not fly-by topology. If not, then how are these two slots on each channel connected to CPU?


      Thank you.