3 Replies Latest reply on Aug 10, 2016 2:29 PM by allan_intel

    Skylake USB 3.0 (xHCI) Controller & USB 2.0 (EHCI) implementation




      I'm wondering about the implementation of the single xXHCI controller on the Skylake chipets. If I recall correctly, the 8 series had 1 xHCI controller and two eHCI controllers for usb 2.0. From what I can remember, bandwidth aside, eHCI was said to be able to support more devices (something to do with devices & endpoints I think?). Now, 1 xHCI controller along with 2 eHCI ones gave us a certain amount of resources, now that eHCI has been removed, have extra xHCI controllers been added? or has anything been changed on the xHCI controllers to basically make up for the removal of eHCI? I looked through the datasheet of the 100 series chipset, but there was no detailed of the PCH like what is available for the 8 series chipset, so if anyone could shed some light on how USB is implemented in Skylake, it would be greatly appreciated.