5 Replies Latest reply on Jun 21, 2016 1:44 PM by cvare

    NUC6I7KYK Why all IO are connected through PCH?

    ErinAdreno

      If you look at this product description page: http://www.intel.com/content/dam/support/us/en/documents/boardsandkits/NUC6i7KYK_TechProdSpec03.pdf

      On page 13, all the IO are connected through PCH, which is behind the limited bandwidth of DMI3.0.

      There are 2 M.2 x4 slots, which has around 2 times the DMI3.0 bandwidth. As well as the thunderbolt 3 port.

      While the native PCIe lanes (ones from CPU uncore) are remain unused, all the stress are put onto the chipset. I can understand that the Sata protocol requires PCH to do the work, but the thunderbolt doesn't make sense. Why Intel configure its own product in this awkward way?

        • 1. Re: NUC6I7KYK Why all IO are connected through PCH?
          femton

          Similar question was posed in Anandtech's review of the Skull Canyon and there were some arguments in the comments defending Intel's approach, but this question is interesting and it would be good to have Intel's answer. Please Intel!

          • 2. Re: NUC6I7KYK Why all IO are connected through PCH?
            Intel Corporation
            This message was posted by Intel Corporation on behalf of

            Hi All,
             
            Intel® NUC Kits are designed to save energy plus the air flow inside the case is limited, so Intel took the decision to use SOC (system on a chip) processors equal to tablets.
             
            Regards,
            Mike C

            • 3. Re: NUC6I7KYK Why all IO are connected through PCH?
              Lokutos

              Intel Corporation wrote:

               

              Hi All,

              Intel® NUC Kits are designed to save energy plus the air flow inside the case is limited, so Intel took the decision to use SOC (system on a chip) processors equal to tablets.

              Regards,
              Mike C

               

              Um, what?

              This question is about the i7 KYK NUC, which is *not* a SoC. There is a separate PCH. Also, the question is not about SoC or not. This doesn't actually have anything to do with that question. Did you even understand what the nature of the original question was?

              The question was why the CPUs PCIe lanes are not used for high-speed I/O such as Thunderbolt (at the very least). Instead everything is funneled through DMI, even Thunderbolt, but also 2 x 4 M.2 PCIe lanes etc. From a performance point of view this doesn't make sense as using DMI for everything limits the total performance of all I/O (2x M.2, SATA, USB 3.0, Thunderbolt) to roughly 4 PCIe 3.0 lanes, i.e. about 4 GiB/s. TB alone would be able to saturate that. Add M.2, USB, etc. and you have a nice bottleneck. The reason for this is unclear as the CPU does have 16 (or so) PCIe lanes directly accessible, so it would've been basically for free to use those.

              • 4. Re: NUC6I7KYK Why all IO are connected through PCH?
                ErinAdreno

                I'm sorry but I don't think 6770HQ has an option to be configured as an SoC or the H170 "Controller Hub" is on the same PCB with cpu die. Although that would be a nice feature.

                Anyway, thanks for the reply.

                • 5. Re: NUC6I7KYK Why all IO are connected through PCH?
                  cvare

                  You are correct, with the S and H CPU SKUs the PCH is separated from the CPU by the DMI interface.  To answer your original question, after talking to the engineers, due to the size and compatibility this is what worked best for the KYK NUC.