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Have you had a look at the 'SPI' example provided in ISSM ? This includes an example of how to set the Frame Size - 8-bit in this case. Is this what you are looking for ?
/* Initialise SPI configuration */ cfg.frame_size = QM_SPI_FRAME_SIZE_8_BIT; cfg.transfer_mode = QM_SPI_TMOD_TX_RX; cfg.bus_mode = QM_SPI_BMODE_0; cfg.clk_divider = SPI_CLOCK_DIV; qm_spi_set_config(QM_SPI_MST_0, &cfg);
The QMSI API documentation has some further information and is available within the ISSM package - or can be downloaded here Download Intel® Quark™ Microcontroller Software Interface
I had seen that ISSM example. Digging deeper I see that cfg.frame_size sets the "Data Frame Size in 32-bit mode (DFS_32)" field in Control Register 0 (CTRLR0). It's the description of this field that had/has me confused. Maybe it's just me, but I don't find it particularly clear, especially the part I've bolded. Especially given that I can find no other reference to SSI_MAX_XFER_SIZE anywhere in the D2000 documentation.
Used to select the data frame length in 32 bit mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32-bits, the receive data is automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. Transmit data must be right-justified by the user before writing into the transmit FIFO. The transmit logic will ignore the upper unused bits when transmitting the data.
As an example contrast this with the Data Size Select (DSS) field of SPI Control Register 0 (SSCR0) for the X1000 (see section 20.5.1 on page 807 here: http://www.intel.ie/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf).
All that said, it's not going to worry me for now. I was just grasping at straws that the word size might be causing a timing issue I'm seeing when trying to communicate with another MCU over SPI but I'll look elsewhere for the issue instead.