1 Reply Latest reply on Jun 1, 2016 1:31 PM by Intel Corporation

    Asymmetrically memory characteristics setup in Xeon system

    OhDDD

      I try to build the asymmetric memory environment in Xeon E5 2650 v2, dual socket environment.

      In the case of memory, 4-channel for each socket was constructed using DDR3 1600MHz 16GB.

      Here, I want to control asymmetrically the bandwidth and latency of memory  for each socket or channel.

      I want to know whether it is possible to the above-mentioned circumstances,

      please tell me if there is a way to control the bios level or os level.

       

      Please tell me further whether it is possible to change the frequency characteristics of the CPU

      and it is possible to control the RW_LB attr in CSR register.

       

       

      HELP!

      Thanks in advance!