All changes seem to be made within the accepted paramenters.
A couple of questions, why do you set 0x3 as .active_slot_map? How did you enabled muxing for I2S, did you follow any guide? What are the contents of your /usr/share/alsa/alsa.conf file?
What steps did you follow to recompile the kernel?
why do you set 0x3 as .active_slot_map?
I just reffered from the post I've mentioned above , should i change it to some other value for I2S operation ?
How did you enabled muxing for I2S, did you follow any guide?
I configured the pins properly cz I can see the PCM data output properly so I assume all the pin muxing and pull configurations are correct
What are the contents of your /usr/share/alsa/alsa.conf file?
I changed the
Take a look at this link https://github.com/ZenfoneArea/android_kernel_asus_zenfone5/blob/master/linux/kernel/sound/soc/intel/platform-libs/controls_v2_dpcm.c . In the static const struct sst_ssp_config function are described the [SST_SSP0], [SST_SSP1] and [SST_SSP2].
Can you try to try the SSP2 port tested configuration from the Audio setup guide section 2.1.3.
The Audio setup guide can be found here http://www.intel.com/content/www/us/en/support/boards-and-kits/000005983.html .
What is your main goal of changing the original [SST_SSP2], to use .ssp_protocol = SSP_MODE_I2S?
What I found in the link was the default configuration of Edison Image, (what we can see in controls_v2_dpcm.c) and it is in dpcm mode. So that Edison outputs PCM data as 4 slot TDM in 24 bits mode with 48Khz sampling rate .
What I'm trying to do is to output I2S data via I2S_2 interface so the configuration has to be changed from PCM to I2S.
Any thoughts how to configure for that ?
Referring to same issue as mentioned by Hari.
We are using MAX98357A chip as codec. This chip supports two modes of operation.
1. TDM mode - MAX98357A supports 16/32 bit , 8 channel data in this mode. It seems to be quite important for this codec that the number of channels is set to 8 and does _not_ seem to support less than that many slots. So there should be either 16x8 or 32x8 bclk clock cycles between each FS sync pulses. We tried to modify the Kernel to output data in this format but was not successful. We had raised this issue in the following thread - PCM - BLCK inaccurate
2. I2S mode - standard I2S protocol data in 16/24/32 bit frames. For this we did the modifications as Hari mentioned above. This is also not been successful yet. We are not seeing any data in the TXD line.
Please advise if you have any comments on this.
Have you tried the lookback test? You can check how to do loopback tests on the Audio Guide https://software.intel.com/en-us/articles/intel-edison-audio-setup-guide-0
Let us know your results.