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I found that integrated memory controller of Intel Xeon E5-2600 supports DDR4 ALERT_n signal for Parity error. Does it support ALERT_N for CRC error also?
I also found that some Intel processors have limited support of ALERT_n signal . Their datasheets say following:
"Alert_n: This signal is used at command training only. It is getting the Command and Address Parity error flag during training".
Does it mean that a memory controller would get the signal only during BIOS initialization and would ignore it after, even a DIMM module asserts the signal?