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I'm currently developing a system that might have to use several high bandwidth USB 3.0 devices (Framegrabbers, Flash Drives, Ethernet Adapters) in conjunction with a Intel Series 100 Chipset (and a Skylake i5 processor). The DMI 3.0 link between PCH and CPU is not expected to be blocked or even remotely saturated by any other devices (PCIe 3.0) connected to it.
Having studied the datasheet for the chipset family and the xHCI Host Controller standard, I learned that each USB port provided by the chipset is connected to
the PCH via a HSIO lane and that the xHCI Host Controller would theoretically allow a "model where the bandwidth of a single USB is shared across all its root hub ports, a “bus per port” model where the full bandwidth of a USB is available on every root hub port, or any combination in between". The Series 100 Chipset datasheet states about the xHCI controller implementation in this chipset family that "transfers up to 5Gbit/s are allowed" which does not state whether this bandwidth is available at each port (quite unlikely I guess), distributed among all ports or something in between.
So the question is:
What is the maximum simultaneous bandwidth across all USB 3.0 SuperSpeed connections that I can expect using a Intel Series 100 Chipset xHCI controller in conjunction with several USB 3.0 devices connected to it? Can I expect to have more than the bandwidth of a single USB 3.0 SuperSpeed link (5 Gbit/s) available across all USB 3.0 ports? If yes how much?
Thanks in advance for your help!