7 Replies Latest reply on Jun 23, 2016 10:23 PM by Intel Corporation

    i210 FLUPD bit set by write to EEWR? / datasheet description for EELOADCTL and EELOADERR

    Lo2

      Hello,

       

      I've got an i210 connected to an SoC and for production I'd like to write the external eeprom via PCIe:

      - I map the config space and access the IO area via the config space registers 0x98/0x9C

      - The semaphore and sync between FW/SW seems to work

      - I write the config (0x80 16bit words) to the SRAM and can read it back, checksum is 0xbaba

       

      Triggering the flash write via FLUPD fails: FLUPD is already set to one by the first write to the SRAM?

      After the first SRAM write via EEWR, EEC reads: 0x482a00, is this correct?

      When will FLUPD be reset? By whom?

       

       

      Also I'd like some more documentation on two registers:

      Chapter 8.4.2 describes EELOADCTL:

      This register provides software EEPROM-mode load status.

      All bits are RW to FW, RO to host - excepted to bit 12.

      Then it gives a short table for bit0 all ohters are reseved, a second, completely different table describes bits 0:32.

      In chapter 8.4.5 EELOADCTL is described a second time with a single sentence.

      EELOADERR is in chapter 8.4.4 but there's no description of the bits (table missing?)

       

      Can you please provide me the missing/correct tables for these registers?

       

      Best regards,

      Lo