5 Replies Latest reply on Apr 13, 2016 8:46 AM by Intel Corporation

    SOC POWER Sequence mismatch between PDG and Ref Design   : PDG  :  quark-x1000-platform-design-guide_003.pdf  Page 98

    MNKR

      Hi Team,

       

      I am working QUARK SOC.Below is my clarification on Power sequencing.

       

      I have observed SOC POWER Sequence mismatch between PDG and Ref Design   :

       

      Below are the reference document names and attached block diagrams for your reference.

       

      PDG  : quark-x1000-platform-design-guide_003.pdf  Page 98  and

       

      Ref design: 545112_KipsBay_FabD_Schematics_Rev1_0.pdf

       

       

      I will provide you one example where I see mismatch,

       

      TPS652510 is generating 3 outputs which are V3P3_S5,V1P0_S5 and V1P5_S5 In PDG where as in ref-design V3P3_S5,V1P0_S0 and V1P5_S5. I see major mismatch in V1P0_S5 & V1P0_S0.And I see V1P0_S5 in PDG block diagram it is interfaces to SOC but not shown where it is getting connected on SOC.

       

      Could you please check and let me know which one to follow PDG or reference design.

       

       

      Thanks

      Narendra