5 Replies Latest reply on Apr 4, 2016 2:11 PM by Amy_Intel

    Missing TSC deadline interrupt after suspend/resume and using the TSC_ADJUST MSR

    WernerH

      We miss a TSC deadline interrupt after suspend/resume and using the TSC_ADJUST MSR.

      Scenario:

      1. system suspend (ACPI S3)

      2. system resume

      3. synchronize TSC across cores via TSC_ADJUST MSR

      4. program TSC-Deadline timer with deadline=1

      => interrupt does not trigger and TSC_DEADLINE reads continue to return 1

       

      Note: this problem does not occur always and it requires the following preconditions:

      - suspend-resume cycle

      - using the TSC_ADJUST MSR instead of writing the TSC MSR directly (adjustments leads to better synchonization of the TSCs)


      We can increase the probability of failure by introducing an idle loop between 3 and 4 e.g.,

      while (rdtsc < "10s delay") nop;

       

      I would like to know if we are facing a hardware bug. Spec updates regarding missed deadline interrupts with timed MWAIT could be related.