Missing TSC deadline interrupt after suspend/resume and using the TSC_ADJUST MSR

[WHaas1]

We miss a TSC deadline interrupt after suspend/resume and using the TSC_ADJUST MSR.

Scenario:

1. system suspend (ACPI S3)

2. system resume

3. synchronize TSC across cores via TSC_ADJUST MSR

4. program TSC-Deadline timer with deadline=1

=> interrupt does not trigger and TSC_DEADLINE reads continue to return 1

Note: this problem does not occur always and it requires the following preconditions:

- suspend-resume cycle

- using the TSC_ADJUST MSR instead of writing the TSC MSR directly (adjustments leads to better synchonization of the TSCs)

We can increase the probability of failure by introducing an idle loop between 3 and 4 e.g.,

while (rdtsc < "10s delay") nop;

I would like to know if we are facing a hardware bug. Spec updates regarding missed deadline interrupts with timed MWAIT could be related.

[KTran10]

What kind of CPU?

[WHaas1]

We saw it on a couple different machines. We ran our detailed experiments on an i7-5775c and we just received our first bug report from the field from an i7-5600u. All sightings we analyzed so far are from Broadwell-family processors.

[KTran10]

There is errata on Xeon E5 series relate to TSC. You might look into specification update for that processor family

[WHaas1]

I am aware of several errata, in particular the one referring to a lost TSC deadline interrupt after a timed-MWAIT. Since suspend&resume and MWAIT trigger similar sleep state transitions I got wary about a potential hardware bug. Only Intel can resolve this, however their own support engineers recommended posting in this forum to get an answer.

[Amy_C_Intel]

Hello, All:

Thank you for your feedback.

Regards,