Thanks INTEL, but a third party program gave just the answer I nedded.
The Level 1 cache, of 32 KB x2 (Instructions + Data) per CORE is 4 Way associative.
The Level 2 cache, of 256 KB per CORE is 8 Way associative.
The Level 3 cache of 8 MB for all Cores is 16 way associarive.
The cache system is inclusive and implements writethrough policy.
About the clock cicles, I had no answer but I logically presume that, beeing included in CPU chip and so having the same clock frequency they can only be of one clock cicle each one. Only if you have lattchs in the middle of the circuitry, which I don´t see how.
It remains one doubt. Something INTEL doesn't mention in its specifications. I don't even ask if there exists, just their lenghth. I'm talking about TLB (Translation Lookaside Buffer) or translation table cache of virtual to physycall adresses and about cache of Table of Pages.
These last questions remain unclear to me.