1 Reply Latest reply on Apr 21, 2010 10:26 AM by JoaoMOS

    I7 920 Cache memory


      I´m looking for the knowledge of cache system  organization on I7 processors. If any Intel developer can help me I should like to  know:
      The type of organization of the different levels of cache,  i.e., if they are associative, direct mapped or N set associative.
      The  answer in clock cycles of a Cache reading. I suppose that level 1 will  be read in 1 clock cycle. And what about cache Level 2 and Level 3?
      Is  the memory interface which generates the Wait State if there is a cache  miss on Level 1 or is Level 1 by itself?
      Are the different levels of  cache inclusive or exclusive?
      The policy of writing is Write through  or write back?

      Why I7 and these questions? I own an I7 920 CPU and are trying to best know some aspects.

      I post this question for the second time because it was placed as answered before.

        • 1. Re: I7 920 Cache memory

          Thanks INTEL, but a third party program gave just the answer I nedded.

          The Level 1 cache, of 32 KB x2 (Instructions + Data) per CORE is 4 Way associative.

          The Level 2 cache, of 256 KB per CORE is 8 Way associative.

          The Level 3 cache of 8 MB for all Cores is 16 way associarive.

          The cache system is inclusive and implements writethrough policy.


          About the clock cicles, I had no answer but I logically presume that, beeing included in CPU chip and so having the same clock frequency they can only be of one clock cicle each one. Only if you have lattchs in the middle of the circuitry, which I don´t see how.


          It remains one doubt. Something INTEL doesn't mention in its specifications. I don't even ask if there exists, just their lenghth. I'm talking about TLB (Translation Lookaside Buffer) or translation table cache of virtual to physycall adresses and about cache of Table of Pages.

          These last questions remain unclear to me.