Do you know if there are any plans on updating the I2S support in the BSP? I find it very limiting that the Audio DSP has to be master of the I2S bus since that excludes running the codec with an external low jitter clock.
Also the Audio Setup Guide document seems to give even more restrictions that I'm not sure why they are there considering the HW support. E.g
1. HW supported audio configurations only lists sampling frequency up to 48KHz while the HW spec is up to 192KHz
2. The SW supported configuration of SSP2 only lists 48kHz and nothing else, what is the result of this?
Can we expect some updates in the I2S area to actually be able to utilize the HW in front of us? Feels shaky though that the BSP releases are years apart for such a young HW module.
Thank you for a quick reply. I truly hope some updates can be made in this area in the foreseeable future. What about the restrictions in the document that I listed, do they imply that we can only use a sample rate of 48kHz due to SW limitations while we could e.g. use 44.1kHz from w HW point of view (still be limited by the SW limitation though)?
Im the meantime, is there any low level documentation of the SOC used in Edison (for e.g. registers, DMA capabilities/setup etc for the different HW functions) and for the Audio DSP that is referred to in the Audio Setup Guide?
As stated in the guide, the values listed are the tested sampling rates. These values are 8, 16, 44.1 and 48 kHz. It should be possible to work with higher sampling values because the hardware allows for higher frequency sampling however the values not listed in the guide are not tested.
Regarding the low level documentation unfortunately the only documentation available is the one in the site. Detailed documentation of low level capabilities of the SoC is not available.