1 Reply Latest reply: Apr 17, 2012 3:08 PM by Alvaro_Intel RSS

TLB entries, page faults and cached paging structures

cwillems Community Member
Currently Being Moderated

Hi,

 

I have a few questions on which I was not able to find consistent answers in the Intel specs and/or on the web.

It would be great if someone could help me out with them:

 

- in general a TLB entry is created after a successful address translation. however, does this also happen if the resulting memory

is not accessible due to access protections (=> page fault)? I mean: the address translation itself worked properly ...

 

- is an existing TLB entry invalidated if a page fault occurs for that address? Is there different behavior for a) no memory mapped

or b) an access protection occurs ?

 

- besides the TLB entries: are the PDE/PTEs also stored (as regular data) in the L1/L2/LLC Caches? Or is there an additional cache

for the paging structures?

 

- if so: are there any circumstances under which the MMU flushes already cached PDE/PTE entries from the L1/L2/LLC caches?

 

Thanks a lot for your help in advance ...

cw

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