The L2 is write-back only. It cannot be configured for write-through. It is not write allocate. Sometimes people call a cache that is not write allocate, write-around. Look at http://communities.intel.com/docs/DOC-5753 for more information about L2.
L2 is unified, but L1 has an instruction and a data cache. The instruction cache is read-only, so it doesn't have a write policy. Look at EAS Table 12 for L1 data write policy. It can be write-back or write-through. What is it by default? I'm not sure. Write-back, I think. It is not write allocate.
Yes, hardware just knows about MPBT memory. Default for shared off-chip memory is not cacheable. With SCC Linux, whether it is cacheable or not depends on whether you get the memory through /dev/rckncm or /dev/rckdcm. (ncm = non-cacheable memory; dcm = definitely cacheable memory.)
There is no flush instruction for L2. There is no snooping. Look at Marcbug 195 for information about how to deal with cacheable shared memory.