3 Replies Latest reply on Jun 9, 2011 9:13 AM by tedk

    (modified) PC54C internal data cache (L1d)


      Hi all,

        I've got a tecnical question about L1 data cache in SCC cores.


      On write miss, what is the L1 policy? Write-allocate or no write-allocate?

      I think it should be no write-allocate (so only read misses cause data to be loaded in L1 cache), because when we use MPBT shared memory (i.e. MPB) and we want to write something, we also want to be sure that the write operation effectively reach the shared memory, so that the other core can read what I have just written.


      Of course the hardware don't know the difference between shared memory and private memory, it just know the difference between MPBT memory and

      non-MPBT memory, right?

      So hardware could behave in a different way for this two types.


      So, in general, what is the write miss policy?


      Second question: if I'm working with MPBT memory, can I use both write-through and write-back policies as I would do in the old P54C processor? Or are there

      some limitations for MPBT types (apart from the fact that MPBT memory bypasses L2 and uses the write-combine buffer)?